ST7L15 datasheet(90/138 Pages) STMICROELECTRONICS

90 / 138 page

ST7L15, ST7L19

90/138

10-BIT A/D CONVERTER (ADC) (cont’d)

11.5.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by soft-

ware reading the ADCDRH register.

0: Conversion is not complete

1: Conversion complete

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software. It is used

together with the SLOW bit to configure the ADC

clock speed. Refer to the table in the SLOW bit de-

scription (ADCDRL register).

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: A/D converter is switched off

1: A/D converter is switched on

Bits 4:3 = Reserved (must be kept cleared)

Bits 2:0 = CH[2:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

*The number of channels is device dependent.

Refer to the device pinout description.

DATA REGISTER HIGH (ADCDRH)

Read Only

Reset Value: xxxx xxxx (xxh)

Bits 7:0 = D[9:2] MSB of Analog Converted Value

AMP CONTROL/DATA REGISTER LOW (AD-

CDRL)

Read/Write

Reset Value: 0000 00xx (0xh)

Bits 7:5 = Reserved (forced by hardware to 0)

Bit 4 = Reserved (must be kept cleared)

Bit 3 = SLOW Slow mode

This bit is set and cleared by software. It is used

together with the SPEED bit in the ADCCSR regis-

ter to configure the ADC clock speed as shown on

the table below.

Note: Max fADC allowed = 4 MHz (see section

13.11 on page 122)

Bit 2 = Reserved (must be kept cleared)

Bits 1:0 = D[1:0] LSB of Analog Converted Value

EOC

SPEED ADON

CH2

CH1

CH0

Channel Pin*

CH2

CH1

CH0

AIN0

000

AIN1

001

AIN2

010

AIN3

011

AIN4

100

AIN5

101

AIN6

110

SLOW

fADC

SLOW SPEED

fCPU/2

fCPU

fCPU/4

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