UPD17062 datasheet(53/298 Pages) RENESAS

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µPD17062

Table 7-2 Modification of the Data Memory Address and Indirect Transfer Address by the Index Register

and Data Memory Row Address Pointer

BANK

: Bank register

: Index register

IXE

: Index enable flag

IXH

: Bits 10 to 8 of the index register

IXM : Bits 7 to 4 of the index register

IXL

: Bits 3 to 0 of the index register

: Data memory address specified with mR and mC

: Data memory row address (high order)

: Data memory column address (low order)

: Data memory row address pointer

MPE : Memory pointer enable flag

: General-purpose register column address

: General-purpose register pointer

(

×)

: Contents addressed by

b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0

IXE

MPE

BANK

(r)

BANK

(r)

IXH, IXM

Logical

General-purpose register address

specified with r

Data memory address specified with m

Indirect transfer address specified with @r

Bank

Row

address

Column

address

Bank

Row

address

Column

address

Bank

Row

address

Column

address

Same as

above

Same as

above

Same as

above

Same as

above

Same as

above

Logical

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