LXT971ABC datasheet(25/90 Pages) INTEL

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver

Datasheet

Document #: 249414

Revision #: 002

Rev. Date: August 7, 2002

3.2.3.1.3 MII Interrupts

The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in Figure 6. The

LXT971A also provides two dedicated interrupt registers. Register 18 provides interrupt enable

and mask functions and Register 19 provides interrupt status. Setting Register bit 18.1 = 1, enables

the device to request interrupt via the MDINT pin. An active Low on this pin indicates a status

change on the LXT971A. Interrupts may be caused by four conditions:

• Auto-negotiation complete

• Speed status change

• Duplex status change

• Link status change

3.2.3.2

Hardware Control Interface

The LXT971A provides a Hardware Control Interface for applications where the MDIO is not

desired. The Hardware Control Interface uses the three LED driver pins to set device configuration.

Refer to the Hardware Configuration Settings section on page 30 for additional details.

Figure 5. Management Interface Write Frame Structure

MDC

MDIO

(Write)

32 "1"s

Preamble

Op Code

PHY Address

Turn

Around

D15

D14

Data

Idle

Write

Figure 6. Interrupt Logic

NAND

Even X Mask Reg

Even X Status Reg

Force Interrupt

Interrupt Enable

AND

Interrupt Pin (MDINT)

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