Nexperia

74ALVC32

Quad 2-input OR gate

4. Functional diagram

mna242

1A

1B

1Y

2

1

3

2A

2B

2Y

5

4

6

3A

3B

3Y

10

9

8

4A

4B

4Y

13

12

11

Fig. 1. Logic symbol

mna243

3

≥1

≥1

≥1

≥1

2

1

6

5

4

8

10

9

11

13

12

Fig. 2. IEC logic symbol

mna241

A

B

Y

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74ALVC32

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

aaa-032403

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14) and

SOT402-1 (TSSOP14)

aaa-032404

74ALVC32

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

4B

1B

GND(1)

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND

Fig. 5. Pin configuration SOT762-1 (DHVQFN14)

74ALVC32

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 30 April 2021

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