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MA2909/11
8
Table 8: Cycle Time and Clock Charcteristics
Time
Minimum clock low time
15
Minimum clock high time
15
Cn + 4
40
35
30
25
40
-
-
45
45
45
Set-up time
10
10
20
20
15
20
20
20
25
Hold Time
10
7
5
10
5
0
0
0
0
From input
RE
RI
PUP
FE
Cn
DI
ORI
S0, S1
ZERO
Notes:
1. CL < 50pF
2. RL
≥ 680Ω
3. RL
≥ 680Ω, measured 0.5V change in output level
Table 9: Maximum Combinational Propogation Delays
Table 10: Guaranteed Set-up and Hold Times (all in ns)
All times in ns across full voltage and temperature range.
MIL-STD-883, method 5005, subgroups 9, 10 and 11.
Figure 2
Y
35
30
20
-
35
25
25
40
40
50
From input
D1
S0, S1
ORI
Cn
ZERO
OE LOW (enable) (Note 2)
OE HIGH (disable) (Note 3)
Clock: S1S0 = LH
Clock: S1S0 = LL
Clock: S1S0 = HL
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