FAS209 datasheet(2/8 Pages) ETC1

2 / 8 page

FAS209

53209-580-00 C

QLogic Corporation

FAS209 bus conﬁguration is selected by pulling the

MODE pin up or down, as shown in table 1.

Microprocessor Interface

Microprocessor interface to the FAS209 occurs over the

PAD bus or the DB bus. Both interfaces allow the

microprocessor to read and write to all the internal chip

registers, including the FIFO.

In single-bus mode (bus conﬁguration mode 0), the

PAD bus is not used and the microprocessor must arbitrate

with other controllers for use of the DB bus. In split-bus

mode (bus conﬁguration mode 1), the PAD bus is dedicated

to the microprocessor interface.

Pins that support the microprocessor and DMA

interfaces and other chip operations are shown in ﬁgure 2.

DMA Interface

All FAS209 DMA activity occurs over the DB bus. The

path is eight bits wide. The DB bus consists of the data

parity pin DBP0 and data pins DB7-0. Data is transferred

on DB7-0 on writes to and reads from the SCSI bus.

DACK must be active during DMA accesses. The

transfer direction is determined by the type of command

executed by the chip. DBWR strobes data into the chip.

DMA read data is driven by the chip when DACK is true.

Packaging

The FAS209 is available in a 64-pin plastic quad ﬂat

pack (PQFP), part number 2405055; and a thin quad ﬂat

pack (TQPF), part number 2405095. The pin diagrams are

shown in ﬁgures 2 and 4. Package dimensions are shown

in ﬁgures 3 and 5. The FAS209 pins that support

microprocessor interfaces and other chip operations are

shown in ﬁgure 6.

Table 1. Bus Modes

Mode

No.

MODE

Data

DMA

Data

Conﬁguration

DB bus

Single bus, 8-bit

DMA

PAD bus

DB bus

Split bus, 8-bit

DMA

TRANSFER COUNT

SCSI DATA

SCSI CONTROL

DB BUS

PAD BUS

TRANSFER COUNTER

CLK CONVERSION

TEST

CONFIGURATION

SELECT/RESELECT

BUS ID

SELECT/RESELECT

TIMEOUT

SYNC OFFSET/

SYNC ASSERT/

SYNC DE-ASSERT

SYNC PERIOD

COMMAND

INTERRUPT

STATUS

SEQUENCE STEP

FIFO

SEQUENCERS

Figure 1. FAS209 Block Diagram

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