AD9510SLASHPCB datasheet(45/60 Pages) AD

Nome de Peças	AD9510/PCB

Descrição Electrónicos	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

PDF	60 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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45 / 60 page

AD9510

Rev. A | Page 45 of 60

CSB

SCLK

SDIO

tHI

tLO

tCLK

tDS

tDH

BI N

BI N + 1

Figure 51. Serial Control Port Timing—Write

Table 22. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

CSB

CSB TOGGLE INDICATES

CYCLE COMPLETE

16 INSTRUCTION BITS + 8 DATA BITS

COMMUNICATION CYCLE 1

COMMUNICATION CYCLE 2

TIMING DIAGRAM FOR TWO SUCCESSIVE CUMMUNICATION CYCLES. NOTE THAT CSB MUST

BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.

tPWH

SCLK

SDIO

Figure 52. Use of CSB to Define Communications Cycle

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