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4LS

Digital Interface

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

114

│ 55

Figure 79 shows the block diagram of the SPI.

Figure 79:

SPI Functional Block

This interface uses the following signals.

Figure 80:

SPI Signals

Signal

Function

Force Update

Forces the write of the latest data to registers, transferring from shadow to effective memory

MISO

Master In, Slave Out

MOSI

Master Out, Slave In

N_CS

Low active chip select

N_RST_SPI

Low active reset for both SPI interface and all registers

SCLK

Serial interface clock frequency

TSCLK

Serial interface clock period

The command word has a length of 16 bits that contains the address of the register and the data. The

SCLK signal frequency, should not be higher than ¼ of main clock up to 12.5 MHz i.e., if MCLK is

10 MHz, SCLK should be defined to a maximum of 2.5 MHz, however if MCLK is >50 MHz, SCLK

should not exceed 12.5 MHz.

For read and write operations the data is sent from MSB to LSB.

4LS SPI Functional Block

Control Block

N_CS

SCLK

N_RST_SPI

Input Block

Output Block

MOSI

MISO

Read Block

Registers

Force_Update

MCLK

DATA

ADDRESS

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