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4LS

Functional Description

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

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Equation 2:

�� = �� + �� + �� = �� + ��_��

Figure 59:

Data and VTS Clocks

Readout Mode

Data (clocks)

Minimum LVAL Low

Period (clocks)

Minimum Readout Time

(clocks)

1-To-1

644

670

2-To-1

1288

1318

4-To-1

2576

2614

7.11.3

ADC Time

The ADC time depends on the sensor configuration (internal or external START_AD, ADC stabilization

on or off, ADC end of range, output mode).

Note that End of Range (EOR) value, that gives the maximum EOR level, is performed using 10-bit.

Therefore, the two LSBs are hardwired fixed at '1' and the other 8 bits come from the End of Range

Figure 60:

End of Range Value

Value Defined by End of Range Register

Hardwired Fix Values

The following formula presents the relationship between the value on the register and the number of

clock cycles.

Equation 3:

�� = (�� × 4) + 3

Figure 61:

ADC Time According to the Sensor Configuration

Start AD

ADC Stabilization

Output Mode

ADC Time [clocks]

Auto Start AD OFF

Status2Reg[4] = ' 0 '

ADC Response

Stabilization OFF

Status6Reg[0] = ' 0 '

8-bit mode

Status2Reg[3] = ' 1 '

24 + ROUNDUP(EOR_value + 1) = 280(1)

12-bit mode

Status2Reg[3] = ' 0 '

24 + ROUNDUP((EOR_value + 1) / 1.5) = 707(1)

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