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AD8336ACPZ-R7 Folha de dados(PDF) 24 Page - Analog Devices |
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AD8336ACPZ-R7 Folha de dados(HTML) 24 Page - Analog Devices |
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24 / 28 page ![]() AD8336 Rev. 0 | Page 24 of 28 Circuit Configuration for Inverting Gain The preamplifier can also be used in an inverting configuration, as shown in Figure 81. PRAO 34dB AD8336 PREAMPLIFIER INPP 4 5 + – 8 9 GAIN = 9.6dB INPN CIRCUIT CONFIGURATION FOR INVERTING GAIN RFB1 100Ω RFB2 301Ω 13 VPOS VNEG 10 VOUT 1 +5V –5V PWRA 2 3 VCOM –60dB TO 0dB Figure 81. Circuit Configuration for Inverting Gain The same considerations regarding total resistance vs. distortion, noise, and power as noted in the noninverting case apply, except that the amplifier can be operated at unity inverting gain. The signal gain is reduced while the noise gain is the same as for the noninverting configuration: 1 2 FB FB R R Gain Signal = and 1 1 2 + = FB FB R R Gain Noise USING THE POWER ADJUST FEATURE The AD8336 has the provision to operate at lower power with a trade-off in bandwidth. The power reduction applies to the preamp and the VGA sections, and the bandwidth is reduced equally between them. Reducing the power is particularly useful when operating with higher supply voltages and lower values of output loading that would otherwise stress the output amplifiers. When Pin PWRA is grounded, the amplifiers operate in their default mode, and the combined 3 dB bandwidth is 80 MHz with the preamp gain adjusted to 4×. When the voltage on Pin PWRA is between 1.2 V and 5 V, the power is reduced by approximately half and the 3 dB bandwidth reduces to approximately 35 MHz. The voltage at pin PWRA must not exceed 5 V. DRIVING CAPACITIVE LOADS The output stages of the AD8336 are stable with capacitive loads up to 47 pF for a supply voltage of ±3 V, and capacitive loads up to 10 pF for supply voltages up to ±8 V. For larger combined values of load capacitance and/or supply voltage, a 20 Ω series resistor is recommended for stability. The influence of capacitance and supply voltage are shown in, Figure 50 and Figure 51, where representative combinations of load capacitance and supply voltage requiring a 20 Ω resistor are marked with an asterisk. No resistor is required for the ±3 V plots in Figure 49, while a resistor is required for most of the ±12 V plots in Figure 51. |
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