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NB2304AI2DG Folha de dados(PDF) 4 Page - ON Semiconductor

Nome de Peças NB2304AI2DG
Descrição Electrónicos  3.3 V Zero Delay Clock Buffer
PDF  10 Pages
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
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NB2304AI2DG Folha de dados(HTML) 4 Page - ON Semiconductor

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Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30 pF load (all devices)
15 pF load (−1, −2)
15
15
133
133.3
MHz
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT = 66.66 MHz
30 pF load
40.0
50.0
60.0
%
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
45.0
50.0
55.0
t3
Output Rise Time
(−1, −2)
Measured between 0.8 V and 2.0 V
30 pF load
2.20
ns
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Rise Time
(−1H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
t4
Output Fall Time
(−1, −2)
Measured between 2.0 V and 0.8 V
30 pF load
2.20
ns
Measured between 2.0 V and 0.8 V
15 pF load
1.50
Output Fall Time
(−1H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
t5
Output−to−Output Skew on same Bank
(−1, −2)
All outputs equally loaded
200
ps
Output−to−Output Skew
(−1H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−1)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−2)
All outputs equally loaded
400
t6
Delay, REF Rising Edge to FBK Rising
Edge
Measured at VDD/2
0
±250
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0
500
ps
t8
Output Slew Rate
Measured between 0.8 V and 2.0 V using
Test Circuit #2
1
V/ns
tJ
Cycle−to−Cycle Jitter
(−1, −1H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
175
ps
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Cycle−to−Cycle Jitter
(−2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
400
ps
Measured at 66.67 MHz, loaded outputs,
15 pF load
375
tLOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
1.0
ms



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