IDTTM

Progammable Timing Control HubTM for Next Gen P4TM Processor

701J—01/25/10

ICS952601

Programmable Timing Control HubTM for Next Gen P4TM Processor

22

PCI_STOP Asserted

SRC_Stop = Tristate, SRC_Pwrdwn = Tristate

PCI_Stop#

1.8mS

PWRDWN#

PCI (Free Running)

CPU (Free Running)

CPU# (Free Running)

SRC (Stoppable)

SRC# (Stoppable)

Notes:

1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#

and PWRDWN#.

2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can

sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming

immediately after the 1.8mS window expires. This applies to all control register bit changes as well.

3. Tristate outputs are pulled low by output termination resistors as shown here.