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AM26LS31C Folha de dados(PDF) 13 Page - Texas Instruments

Nome de Peças AM26LS31C
Descrição Electrónicos  AM26LS31x Quadruple Differential Line Driver
PDF  34 Pages
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Fabricante Electrônico  TI [Texas Instruments]
Página de início  http://www.ti.com
Logo TI - Texas Instruments

AM26LS31C Folha de dados(HTML) 13 Page - Texas Instruments

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AM26LS31
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VCC
0.1uF
Reduce logic
signal trace
where possible
1A
GND
VCC
13
AM26LS31, AM26LS31C, AM26LS31I, AM26LS31M
www.ti.com
SLLS114L – JANUARY 1979 – REVISED OCTOBER 2018
Product Folder Links: AM26LS31 AM26LS31M
Submit Documentation Feedback
Copyright © 1979–2018, Texas Instruments Incorporated
10 Power Supply Recommendations
Place a 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
Noise can often propagate into analog circuitry through the power supply of the circuit. Bypass capacitors are
used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
11.2 Layout Example
Figure 14. Layout Recommendation



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