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ICS93705 Folha de dados(PDF) 1 Page - Renesas Technology Corp

Nome de Peças ICS93705
Descrição Electrónicos  DDR Phase Lock Loop Zero Delay Clock Buffer
PDF  9 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS93705 Folha de dados(HTML) 1 Page - Renesas Technology Corp

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ICS93705
0418D—04/28/05
Block Diagram
DDR Phase Lock Loop Zero Delay Clock Buffer
Pin Configuration
48-Pin SSOP
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
•
Low skew, low jitter PLL clock driver
•I
2C for functional and output control
•
Feedback pins for input to output synchronization
•
Spread Spectrum tolerant inputs
•
3.3V tolerant CLK_INT input
Switching Characteristics:
•
PEAK - PEAK jitter (66MHz): <120ps
•
PEAK - PEAK jitter (>100MHz): <75ps
•
CYCLE - CYCLE jitter (66MHz):<120ps
•
CYCLE - CYCLE jitter (>100MHz):<65ps
•
OUTPUT - OUTPUT skew: <100ps
•
Output Rise and Fall Time: 450ps - 950ps
•
DUTY CYCLE: 49% - 51%
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
N/C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
VDD
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
SDATA
N/C
VDD
FB_OUTT
N/C
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
FB_INT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Functionality
FB_INT
CLK_INT
PLL
SCLK
SDATA
Control
Logic
FB_OUTT
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
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