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AS7341

Datasheet

• PUBLIC

DS000504

• v3-00 • 2020-Jun-25

│ 42

SP_TH_L_MSB Register (Address 0x85)

Figure 58:

SP_TH_L_MSB Register

Addr: 0x85

SP_TH_L_MSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_L_MSB

0x00

Spectral low threshold MSB

This register provides the high byte of the low

interrupt threshold (CH0).

Both SP_TH_L registers are combined to a 16-bit

threshold. If the value captured by channel 0 is

below the low threshold and the APERS value is

reached the bit SP_IEN is set and an interrupt is

generated.

There is an 8-bit data latch implemented that stores

the written low byte until the high byte is written.

Both bytes will be applied at the same time to avoid

an invalid threshold.

Note: The LSB register cannot be changed without

writing to the MSB register. It is recommended to

write to SP_TH_L_LSB and SP_TH_L_MSB within

one I2C command.

SP_TH_H_LSB Register (Address 0x86)

Figure 59:

SP_TH_H_LSB Register

Addr: 0x86

SP_TH_H_LSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_H_LSB

0x00

Spectral high threshold LSB

This register provides the low byte of the high

interrupt threshold (CH0).

SP _TH_H_MSB Register (Address 0x87)

Figure 60:

SP _TH_H_MSB Register

Addr: 0x87

SP _TH_H_MSB

Bit

Bit Name

Default

Access

Bit Description

7:0

SP_TH_H_MSB

0x00

Spectral high threshold MSB

This register provides the high byte of the high

interrupt threshold (CH0).

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