3

ICS1574B

PCLK Programmable Divider

The ICS1574B has a programmable divider (referred to in Fig-

ure 1 as the PCLK divider) that is used to generate the PCLK

clock frequency for the pixel clock output. The modulus of

this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under

register control. The design of this divider permits the output

duty factor to be 50/50, even when an odd modulus is se-

lected. The input frequency to this divider is the output of the

PLL post-scaler described below:

The phase of the PCLK output is aligned with the internal

high frequency PLL clock (FVCO) immediately after the asser-

tion of the PCLKEN input pulse (active low if PCLKEN_POL

bit is 0 or active high if PCLKEN_POL bit is 1).

When PCLKEN is deasserted, the PCLK output will complete

its current cycle and remain at VDD until the next PCLKEN

pulse. The minimum time PCLKEN must be disabled

(TPULSE) is 1/FPCLK.

See Figure 2a for an example of PCLKEN enable (negative

polarity) vs. PCLK timing sequences.

Figure 2a

Figure 2b

s

e

u

l

a

V

K

r

e

d

i

v

i

D

K

L

C

PK

32

a

45

.

3

b

43

55

.

4

65

.

3

a

85

.

5

b

85

0

17

2

15

.

6

a

6

15

.

9

b

6

19

0

22

1

TK = K • TVCO

Td = LOGIC PROP.DELAY TIME

(typically 9ns with a 10pF load on PCLK)

TVCO = 1/FVCO

The resolution of Ton is one VCO cycle.

The time required for a PCLK cycle start following a PCLKEN

enable is described by Figure 2b and the following table:

Typical values for Tr and Tf with a 10pF load on PCLK are

1ns.