EB632 datasheet(25/112 Pages) FREESCALE

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HDI16

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Table 18 shows the result of the four kinds of reset on bits in each of the HDI16 registers accessible to the host

processor. The hardware reset is caused by asserting the RESET signal. The individual reset is caused by clearing

HPCR[HEN].

Table 19 shows the effects of the INIT command in relation to the values of TREQ and RREQ.

Table 20 and Table 21 summarize the effect of RREQ and TREQ on the HREQ and HRRQ signals.

Table 18. Host-Side Registers After Reset

Name

Data

Reset Type

Hardware (HW)

Reset

Individual (IR)

Reset

ICR

All Bits

—

CVR

NMI

HV[0–6]

—

ISR

HREQ

1 if TREQ is set;

0 otherwise

HF[4–7]

—

TRDY

TXDE

RXDF

RX[0–3]

empty

TX[0–3]

empty

Table 19. Effects of the INIT Command

TREQ

RREQ

After INIT Execution

Transfer Direction

Initialized

INIT = 0

None

INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1

Core to host

INIT = 0; ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0

Host to core

INIT = 0; ISR[RXDF] = 0; HSR[HTFE/HTFNF] = 1;

ISR[TXDE] = 1; HSR[HRFF/HRFNE] = 0

Host to/from core

Table 20. TREQ and RREQ Modes (HDRQ = 0) in Non-DMA Mode (HICR=1)

TREQ

RREQ

HREQ Signal

No interrupts (polling)

ISR[RXDF] request (interrupt)

ISR[TXDE] request (interrupt)

ISR[RXDF] and ISR[TXDE] request (interrupts)

Table 21. TREQ and RREQ Modes (HDRQ = 1) in Non-DMA Mode (HICR=1)

TREQ

RREQ

HTRQ Signal

HRRQ Signal

No interrupts (polling)

ISR[RXDF] request (interrupt)

ISR[TXDE] request (interrupt)

No interrupts (polling)

ISR[TXDE] request (interrupt)

ISR[RXDF] request (interrupt)

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