8

604 Hardware Specifications

Preliminary/Subject to Change without Notice

Figure 4 provides the output timing diagram for the 604.

Figure 4. PowerPC 604 Microprocessor Output Timing Diagram

The output specifications of the 604 for both driving high and driving low depend on the capacitive loading

on each output and the drive capability enabled for that output. Additionally, the timing specifications for

outputs driving low also depend on the voltage swing required to drive to 0.8 V (either 5.5 V to 0.8 V or

3.6 V to 0.8 V). Table 7 provides the output AC timing specifications for a 50 pF load. In order to derive the

actual timing specifications for a given set of conditions, it is recommended that IBIS simulation models be

used. Contact the local Motorola or IBM sales office for information on the availability of these models.

SYSCLK

All Outputs

(Except TS,

ABB, DBB,

ARTRY,

XATS, SHD)

TS, XATS

ABB, DBB

ARTRY, SHD

VM = Midpoint voltage (1.4 V)

All output specifications are measured from 0.8 V or 2.0 V of the signal in question to the 1.4 V of the

rising edge of the input SYSCLK

.

12

14

13

15

16

17

VM

VM

15

VM

13

21

19

18

22

20

Notes:

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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