10

PowerPC 602 RISC Microprocessor Hardware Specifications

Figure 2. Input Timing Diagram

Figure 3. Mode Select Input Timing Diagram

11b

HRESET to mode select inputs invalid (input

hold) (for QACK)

0

—

0

—

ns

2,4,5

Notes:

1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the

1.4 V of the rising edge of the input SYSCLK. Both input and output timings are measured at the pin;

see Figure 2.

2. The setup and hold time is with respect to the rising edge of HRESET; see Figure 3.

3. tSYS is the period of the external clock (SYSCLK) in nanoseconds.

4. These values are guaranteed by design, and are not tested.

5. This specification is for configuration-mode only. Also note that HRESET must be held asserted for

a minimum of 255 bus clocks after the PLL-relock time (100

µs) during the power-on reset

sequence.

Table 7. Input AC Timing Specifications (Continued)

Vdd = 3.3

± 10% V dc, GND = 0 V dc, 0 ≤ T

J ≤ 105 °C

Num

Characteristic

66.67 MHz CPU

Clock

80 MHz CPU

Clock

Unit

Notes

Min

Max

Min

Max

VM

SYSCLK

VM = Midpoint Voltage (1.4V)

ALL INPUTS

10a

11a

MODE PINS

HRESET

10b

11b

VM

VM = Midpoint Voltage (1.4 V)

Freescale Semiconductor, Inc.

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