AN1218 datasheet(8/56 Pages) FREESCALE

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Application Note

AN1218 Rev. 2

Condition Code

Overflow Bit V

A summary of the condition code register (CCR) is given below. Unless

otherwise stated, all bits correspond to both CPUs.

Overflow Bit V

This bit is set when a two's-complement overflow has occurred as the

result of an operation. The V bit has been added to the CPU08

condition code register to support two's-complement arithmetic.

Half-Carry Bit H

The half-carry bit is set when a carry has occurred between bits 3 and

4 of the accumulator because of the last ADD or ADC operation. This

bit is required for BCD operations.

Table 2. Addressing Mode Examples

Addressing Mode

Example

Inherent

RSP

Immediate

LDA

#$FF

Direct

LDA

$50

Extended

LDA

$1000

Indexed, no offset

LDA

Indexed, 8-bit offset

LDA

$50,X

Indexed, 16-bit offset

LDA

$0150,X

Relative

BRA

$20

Stack Pointer, 8-bit offset*

LDA

$50,SP

Stack Pointer, 16-bit offset*

LDA

$0150,SP

Memory to memory

ImmDir*

DirDir*

Ix+Dir*

DirIx+*

MOV

#$30,$80

$80,$90

X+,$90

$80,X+

Indexed w/post increment*

CBEQ

X+,LOOP

Indexed, 8-bit offset, w/post increment*

CBEQ

$20,X+,LOOP

New CPU08 addressing modes

Freescale Semiconductor, Inc.

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