MPC9331 REVISION 7 March 11, 2016

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©2016 Integrated Device Technology, Inc.

MPC9331 Data Sheet

3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR

Table 2. Function Table

Control

Default

0

1

REF_SEL

0

PCLK is the PLL reference clock

CCLK is the PLL reference clock

FB_SEL

1

Internal PLL feedback of 8. fVCO = 8 * fref

External feedback. Zero-delay operation

enabled for CCLK or PCLK as reference

clock

PLL_EN

1

Test mode with PLL disabled. The reference clock is

substituted for the internal VCO output. MPC9331 is fully static

and no minimum frequency limit applies. All PLL related AC

characteristics are not applicable.

Normal operation mode with PLL enabled.

PWR_DN

1

VCO

 1 (High output frequency range)

VCO

 2 (Low output frequency range)

FSELA

0

Output divider

 2

Output divider

 4

FSELB

0

Output divider

 2

Output divider

 4

FSELC

0

Output divider

 4

Output divider

 6

OE/MR

1

Outputs disabled (high-impedance state) and reset of the

device. During reset in external feedback configuration, the

PLL feedback loop is open. The VCO is tied to its lowest

frequency. The MPC9331 requires reset after any loss of PLL

lock. Loss of PLL lock may occur when the external feedback

path is interrupted. The length of the reset pulse should be

greater than one reference clock cycle (CCLK or PCLK). Reset

does not affect PLL lock in internal feedback configuration.

Outputs enabled (active)

CLK_STOP[0:1]

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See Table 3

PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.

See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios.