M95M02-DFMN5GSLASHK datasheet(18/45 Pages) STMICROELECTRONICS

Nome de Peças	M95M02-DFMN5G/K

Descrição Electrónicos	2-Mbit serial SPI bus EEPROM

PDF	45 Pages

Scroll/Zoom	100%

Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

Página de início	http://www.st.com

Logo

18 / 45 page

6.5

Read from memory array (READ)

As shown in Figure 13, to send this instruction to the device, chip select (S) is first driven low. The bits of the

instruction byte and address bytes are then shifted in, on serial data input (D). The address is loaded into an

internal address register, and the byte of data at that address is shifted out, on serial data output (Q).

Figure 13. Read from memory array (READ) sequence

If chip select (S) continues to be driven low, the internal address register is incremented automatically, and the

byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the read cycle to be

continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.

The read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur

at any time during the cycle.

The instruction is not accepted, and is not executed, if a write cycle is currently in progress.

M95M02-DR M95M02-DF

Read from memory array (READ)

DS7024 - Rev 13

page 18/45

M95M02-DFMN5G/K Folha de dados(PDF) 18 Page - STMicroelectronics