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LM1229YA Folha de dados(PDF) 21 Page - National Semiconductor (TI) |
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LM1229YA Folha de dados(HTML) 21 Page - National Semiconductor (TI) |
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21 / 27 page ![]() Application Register Detail (Continued) GREEN Gain Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GREEN GAIN 0x01 X GGAIN[6:0] Bits 6–0: Sets the gain level of the green video channel. A value of 0x7F generates the maximum green gain. A value of 0x00 generates the minimum green gain. BLUE Gain Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BLUE GAIN 0x02 X BGAIN[6:0] Bits 6–0: Sets the gain level of the blue video channel. A value of 0x7F generates the maximum blue gain. A value of 0x00 generates the minimum blue gain. CONTRAST Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CONTRAST 0x03 X CONTRAST[6:0] Bits 6–0: Sets the contrast level three video channels. A value of 0x7F generates the maximum contrast. A value of 0x00 generates the minimum contrast. DAC 1 Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC 1 0x04 DAC1[7:0] Bits 7–0: Sets the DAC 1 DC output level at pin 39. A full scale value of 0xFF generates the maximum DC output level. A value of 0x00 generates the minimum DC level. DAC 2 Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC 2 0x05 DAC2[7:0] Bits 7–0: Sets the DAC 2 DC output level at pin 38. A full scale value of 0xFF generates the maximum DC output level. A value of 0x00 generates the minimum level. DAC 3 Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC 3 0x06 DAC3[7:0] Bits 7–0: Sets the DAC 3 DC output level at pin 37. A full scale value of 0xFF generates the maximum DC output level. A value of 0x00 generates the minimum level. BRIGHTNESS Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BRIGHTNESS 0x07 BRIGHTNESS[7:0] Bits 7–0: Sets the brightness level of the RGB outputs. A full scale value of 0xFF generates the minimum DC video black level (darkest). A value of 0x00 generates the maximum DC black level (brightest). OFFSET Control Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OFFSET 0x08 X X X X DC_Offset[3:0] Bits 3–0: Determines the video reference level at the RGB video outputs on pins 57, 58 and 59. A setting of 0xF gives a DC Offset of about 0.5V and 0x0 gives a DC Offset of about 1.4V. GLOBAL Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GLOBAL 0x09 INCR X DCF VB CLAMP HB PSAVE BLANK Bit 7: When set to 0, the I 2C auto increment function is active. When set to a 1, the I2C auto increment function is disabled. In the auto increment mode, a given register can be updated continuously using an ADDR - DATA - DATA - ... - DATA transmission sequence. Bit 5: When set to 0, the outputs of DACs 1–3 are full scale (0V–4.2V). When this bit is a 1, the output DC range is halved www.national.com 21 |
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