AT43USB351M-AC datasheet(29/101 Pages) ATMEL

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AT43USB351M

3302E–USB–7/04

MCU Control Register – MCUCR

• Bit 7, 6 – Res: Reserved Bits

• Bit 5 – SE: Sleep Enable

The SE bit must be set (1) to make the MCU enter the sleep mode when the SLEEP instruc-

tion is executed. To avoid the MCU entering the sleep mode, unless it is the programmer's

purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the

SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode

is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode.

The AT43USB351M does not support the Idle Mode and SM should always be set to one

when entering the Sleep Mode.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-

sponding interrupt mask in the GIMSK is set. The level and edges on the external INT1 pin

that activate the interrupt are defined in the following table:

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask in the GIMSK is set. The level and edges on the external INT0 pin

that activate the interrupt are defined in Table 9.

Bit

$35 ($55)

–

ISC11

ISC10

ISC01

ISC00

MCUCR

Read/Write

R/W

Initial Value

Table 8. INT1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an interrupt request.

Reserved.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

Table 9. INT0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Reserved.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

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