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RA4E2 Folha de dados(PDF) 32 Page - Renesas Technology Corp |
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RA4E2 Folha de dados(HTML) 32 Page - Renesas Technology Corp |
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32 / 90 page ![]() PLLCR.PLLSTP OSCSF.PLLSF PLL clock tPLLWT PLL circuit output Figure 2.10 PLL clock oscillation start timing Sub-clock oscillator output SOSCCR.SOSTP Sub-clock tSUBOSCWT Figure 2.11 Sub-clock oscillation start timing 2.3.3 Reset Timing Table 2.19 Reset timing Parameter Symbol Min Typ Max Unit Test conditions RES pulse width Power-on tRESWP 0.7 — — ms Figure 2.12 Deep Software Standby mode tRESWD 0.6 — — ms Figure 2.13 Software Standby mode, Subosc-speed mode tRESWS 0.3 — — ms All other tRESW 200 — — µs Wait time after RES cancellation tRESWT — 37.3 41.2 µs Figure 2.12 Wait time after internal reset cancellation (IWDT reset, WDT reset, software reset, SRAM parity error reset, SRAM ECC error reset, bus master MPU error reset, TrustZone error reset, Cache parity error reset) tRESW2 — 324 397.7 µs — RA4E2 Datasheet 2. Electrical Characteristics R01DS0413EJ0110 Rev.1.10 Feb 28, 2023 Page 32 of 90 |
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