Rev C 1/5/15

12

LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-LVDS CLOCK

85408 DATA SHEET

Power Considerations

This section provides information on power dissipation and junction temperature for the 85408.

Equations and example calculations are also provided.

1.

Power Dissipation.

The total power dissipation for the 85408 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The

following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

•

Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj =



JA * Pd_total + TA

Tj = Junction Temperature



JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance



JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 70°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.312W * 70°C/W = 91.8°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection



JA by Velocity

Meters per Second

01

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

70°C/W

65.0°C/W

62°C/W