6.42

71321SA/LA and 71421SA/LA

High Speed 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

12

tWC

tWP

tDW

tDH

tBDD

tDDD

tBDA

tWDD

ADDR"B"

DATAOUT"B"

DATAIN"A"

ADDR"A"

MATCH

VALID

MATCH

VALID

R/

W"A"

BUSY"B"

tAPS

(1)

2691 drw 10

tBAA

Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

NOTES:

1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the slave version (IDT71421).

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

Timing Waveform of Write with BUSY(4)

BUSY"B"

2691 drw 11

R/

W"A"

tWP

tWH

tWB

R/

W"B"

(2)

(1)

(3)

,