AX88871AP datasheet(4/30 Pages) ASIX

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AX88871AP Bripeater

ASIX ELECTRONICS CORPORATION

1.0 AX88871A Overview

The AX88871A 10/100Mbps Dual Speed “Bripeater” Controller is “a dual speed

repeater with build in bridge function” It is design for low cost dumb HUB application. The

AX88871A directly supports up-to eight 10/100Mbps automatic links MII interfaces. Maximum

up-to 192 ports can be constructed when using inter-repeater bus horizontally cascades 4

AX88871A and vertically cascades 6 repeaters. When using the legacy method, maximum up-to

64 ports can be constructed when using expansion bus cascades 8 AX88871As. The AX88871A

is designed base on IEEE 802.3u clause 27 “ Repeater for 100Mb/s base-band networks” It is

fully compatible with IEEE 802.3u standard.

All of the ASIX repeater products with the same speeds has the same cascade

methodology. So the AX88871A can cascade with AX88850, AX88860 and AX88870 series

chips. That is ASIX maintain the consistency of the cascade method for all the repeater product

line.

1.1 General Description

The AX88871A Repeater Controller is a subset of a repeater set containing all the

repeater-specific components and functions, exclusive of PHY components and functions. The

AX88871A has only Media Independent Interface (MII) to connect to PHY devices. Other then

AX88850 series chips that has 2 kinds of interfaces. There are Physical coding sub-layer (PCS)

interface and Media Independent Interface (MII).

The AX88871A supports 8 MII interfaces ports, a bridge packet buffer SRAM interface, a

100Mbps port expansion interface and LED display interface.

The AX88871A supports stand along 10/100Mbps dual speed repeater applications. Also

it can expand the ports count via cascade to other AX88850 and AX88860 pure 100Mbps

repeater chips..

The AX88871A has two application mode.

Mode 0

Single chip repeater application.

Mode 1

Multiple chips cascaded repeater application.

AX88871AP Folha de dados(PDF) 4 Page - ASIX Electronics Corporation