Figure 11. Valley skipping algorithm

Valley Locking Mode

VL2H

VL1H

0 us

TDCM

TDCM-max

VVL=0.3V

N=2

N=3

N=4

N=5

N=0 (QR)

DCM Mode

N=1

VL5

VL4

VL3

VL2

VL1

VDCM

VL

6.4

Primary side regulation feature

The HVLED101 can regulate the output voltage of a high power factor flyback stage without the need of an error

amplifier and relevant optocoupler.

6.4.1

PSR operation

An ST proprietary structure is able to measure the output voltage reading the signal present at the ZCD pin during

demagnetization time.

The output voltage measurement is performed in correspondence with the transformer demagnetization instant.

Figure 12. PSR related signal

V drain

VZCD-ARM

VGD

VIN + VR

- VR

TBLANK

DEMAG

TDLY

VZCD-TRiG

VZCD

VIN

VIN

The internal measurement peripheral is active when the switching activity is running and is not frozen by minimum

blanking time or frequency fold-back.

HVLED101

Primary side regulation feature

DS14143 - Rev 2

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