| Os motores de busca de Datasheet de Componentes eletrônicos |
|
MAX9452 Folha de dados(PDF) 4 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
MAX9452 Folha de dados(HTML) 4 Page - Microsemi Corporation |
|
4 / 19 page ![]() Note 1: All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested. Note 2: The VCXO tracks the input clock frequency by ±60ppm. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL’s falling edge. Note 4: CB = total capacitance of one bus line in pF. Tested with CB = 400pF. Note 5: Input filters on SDA and SCL suppress noise spikes less than 50ns. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Serial-Clock Frequency fSCL 2 MHz CS Fall to CLK Rise Setup Time tCSS 12.5 ns DIN Setup Time tDS 12.5 ns DIN Hold Time tDH 0ns CLK High to CS High tCSH 0ns CS Pulse-High Time tCSW 20 ns SERIAL SPI INTERFACE TIMING CHARACTERISTICS (VDD = 2.4V to 3.6V, TA = -40°C to +85°C. See Figure 7 for the timing parameters definition.) High-Precision Clock Generators with Integrated VCXO 4 _______________________________________________________________________________________ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Serial Clock fSCL 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 µs Repeated Hold Time START Condition tHD,STA 0.6 µs Repeated START Condition Setup TimetSU,STA 0.6 µs STOP Condition Setup Time tSU,STO 0.6 µs Data Hold Time tHD,DAT (Note 3) 100 ns Data Setup Time tSU,DAT 100 ns SCL Clock-Low Period tLOW 1.3 µs SCL Clock-High Period tHIGH 0.7 µs Maximum Receive SCL/SDA Rise Time tR 300 ns Minimum Receive SCL/SDA Rise Time tR (Note 4) 20 + 0.1 x Cb ns Maximum Receive SCL/SDA Fall Time tF 300 ns Minimum Receive SCL/SDA Fall Time tF (Note 4) 20 + 0.1 x Cb ns Fall Time of SDA, Transmitting tF,TX (Note 4) 20 + 0.1Cb 250 ns Pulse Width of Suppressed Spike tSP (Note 5) 0 50 ns Capacitive Load for Each Bus Line CB (Note 4) 400 pF SERIAL I2C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS (VDD = 2.4V to 3.6V, TA = -40°C to +85°C. See Figure 4 for the timing parameters definition.) |
|
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |