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XTPS563203DRLR Folha de dados(PDF) 3 Page - Texas Instruments |
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XTPS563203DRLR Folha de dados(HTML) 3 Page - Texas Instruments |
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3 / 32 page ![]() 5 Pin Configuration and Functions VIN SW GND FB EN BST 1 2 3 4 5 6 Figure 5-1. 6-Pin SOT563 DRL Package (Top View) Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME NO. VIN 1 I Input voltage supply pin SW 2 O Switch node connection between high-side NFET and low-side NFET GND 3 — Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive FB to this GND at a single point. BST 4 O Supply input for the high-side NFET gate drive circuit. Connect a 0.1-µF capacitor between the BST and SW pin. EN 5 I Enable input control. Active high and must be pulled up to enable the device. FB 6 I Converter feedback input. Connect to output voltage with feedback resistor divider. www.ti.com TPS563203, TPS563206 SLUSEZ4 – MARCH 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS563203 TPS563206 |
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