LTC2292 datasheet(22/28 Pages) LINER

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LTC2293/LTC2292/LTC2291

229321f

APPLICATIO S I FOR ATIO

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to VDD and OE to VDD

results in sleep mode, which powers down all circuitry

including the reference and typically dissipates 1mW. When

exiting sleep mode it will take milliseconds for the output

data to become valid because the reference capacitors have

to recharge and stabilize. Connecting SHDN to VDD and OE

to GND results in nap mode, which typically dissipates

30mW. In nap mode, the on-chip reference circuit is kept

on, so that recovery from nap mode is faster than that from

sleep mode, typically taking 100 clock cycles. In both sleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA,

SHDNB). Channel A is controlled by SHDNA and OEA, and

Channel B is controlled by SHDNB and OEB. The nap, sleep

and output enable modes of the two channels are completely

independent, so it is possible to have one channel operat-

ing while the other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2293/LTC2292/LTC2291 can

be multiplexed onto a single data bus. The MUX pin is a

digital input that swaps the two data busses. If MUX is High,

Channel A comes out on DA0-DA11, OFA; Channel B comes

out on DB0-DB11, OFB. If MUX is Low, the output busses

are swapped and Channel A comes out on DB0-DB11, OFB;

Channel B comes out on DA0-DA11, OFA. To multiplex both

channels onto a single output bus, connect MUX, CLKA and

CLKB together (see the Timing Diagram for the multiplexed

mode). The multiplexed data is available on either data

bus—the unused data bus can be disabled with its OE pin.

Grounding and Bypassing

The LTC2293/LTC2292/LTC2291 requires a printed cir-

cuit board with a clean, unbroken ground plane. A multi-

layer board with an internal ground plane is recom-

mended. Layout for the printed circuit board should en-

sure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track or

underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

tors must be located as close to the pins as possible. Of

particular importance is the 0.1µF capacitor between

REFH and REFL. This capacitor should be placed as close

to the device as possible (1.5mm or less). A size 0402

ceramic capacitor is recommended. The large 2.2µF ca-

pacitor between REFH and REFL can be somewhat further

away. The traces connecting the pins and bypass capaci-

tors must be kept short and should be made as wide as

possible.

The LTC2293/LTC2292/LTC2291 differential inputs should

run parallel and close to each other. The input traces

should be as short as possible to minimize capacitance

and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2293/LTC2292/

LTC2291 is transferred from the die through the bottom-

side exposed pad and package leads onto the printed

circuit board. For good electrical and thermal perfor-

mance, the exposed pad should be soldered to a large

grounded pad on the PC board. It is critical that all ground

pins are connected to a ground plane of sufficient area.

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