HC705JJ7GRSSLASHD datasheet(169/230 Pages) NXP

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Programmable Timer

Timer Operation During Wait Mode

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

TOF — Timer Overflow Flag

The TOF bit is automatically set when the 16-bit timer counter rolls

over from $FFFF to $0000. Clear the TOF bit by reading the timer

status register with the TOF set and then accessing the low byte

(TMRL, $0019) of the timer registers. Resets have no effect on TOF.

11.9 Timer Operation During Wait Mode

During wait mode, the 16-bit timer continues to operate normally and

may generate an interrupt to trigger the MCU out of wait mode.

11.10 Timer Operation During Stop Mode

When the MCU enters stop mode, the free-running counter stops

counting (the internal processor clock is stopped). It remains at that

particular count value until stop mode is exited by applying a low signal

to the IRQ/VPP pin, at which time the counter resumes from its stopped

value as if nothing had happened. If stop mode is exited via an external

reset (logic low applied to the RESET pin), the counter is forced to

$FFFC.

If a valid input capture edge occurs during stop mode, the input capture

detect circuitry will be armed. This action does not set any flags or wake

up the MCU, but when the MCU does wake up there will be an active

input capture flag (and data) from the first valid edge. If the stop mode is

exited by an external reset, no input capture flag or data will be present

even if a valid input capture edge was detected during stop mode.

11.11 Timer Operation During Halt Mode

When the MCU enters halt mode, the functions and states of the 16-bit

programmable timer are the same as for wait mode described in 11.9

Timer Operation During Wait Mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705JJ7GRS/D Folha de dados(PDF) 169 Page - NXP Semiconductors