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H5TC4G63CFR-RDA Folha de dados(PDF) 29 Page - Hynix Semiconductor

Nome de Peças H5TC4G63CFR-RDA
Descrição Electrónicos  4Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant)
PDF  33 Pages
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Fabricante Electrônico  HYNIX [Hynix Semiconductor]
Página de início  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5TC4G63CFR-RDA Folha de dados(HTML) 29 Page - Hynix Semiconductor

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Rev. 1.4/ Oct. 2015
29
DDR3-1600 Speed Bins
For specific Notes see “Speed Bin Table Notes” on page 31.
Speed Bin
DDR3-1600
Unit
Note
CL - nRCD - nRP
11-11-11
Parameter
Symbol
min
max
Internal read
command to first data
tAA
13.75
(13.125)5,11
20
ns
ACT to internal read or
write delay time
tRCD
13.75
(13.125)5,11
—ns
PRE command period
tRP
13.75
(13.125)5,11
—ns
ACT to ACT or REF
command period
tRC
48.75
(48.125)5,11
—ns
ACT to PRE command
period
tRAS
35
9 * tREFI
ns
CL = 5
CWL = 5
tCK(AVG)
3.0
3.3
ns
1, 2, 3, 4,
8, 12,13
CWL = 6, 7 tCK(AVG)
Reserved
ns
4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1, 2, 3, 8
CWL = 6
tCK(AVG)
Reserved
ns
1, 2, 3, 4, 8
CWL = 7
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1, 2, 3, 4, 8
(Optional)5
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4, 8
CWL = 8
tCK(AVG)
Reserved
ns
4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1, 2, 3, 8
CWL = 7
tCK(AVG)
Reserved
ns
1, 2, 3, 4, 8
CWL = 8
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 9
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1, 2, 3, 4, 8
(Optional)5
CWL = 8
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 10
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1, 2, 3, 8
CWL = 8
tCK(AVG)
Reserved
ns
1, 2, 3, 4
CL = 11
CWL = 5, 6,7 tCK(AVG)
Reserved
ns
4
CWL = 8
tCK(AVG)
1.25
<1.5
ns
1, 2, 3
Supported CL Settings
5, 6, (7), 8, (9), 10, 11
nCK
Supported CWL Settings
5, 6, 7, 8
nCK



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