Data Sheet

ADRF5050

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 14

Figure 3. Pin Configuration (Top View)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

EN

Enable Input. See Table 7 for the truth table and Figure 6 for the interface schematic.

2

V1

Control Input 1. See Table 7 for the truth table and Figure 5 for the interface schematic.

3, 5, 9, 11 to 13, 15 to 17,

19 to 21, 23

GND

Ground. The GND pins must be connected to the RF and dc ground of the PCB.

4

RFC

RF Common Port. No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the

interface schematic.

6

VSS

Negative Supply Voltage.

7

LS

Logic Select Input. See Table 7 for the truth table and Figure 6 for the interface schematic.

8

VDD

Positive Supply Voltage.

10

RF4

RF Throw Port 4. No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the

interface schematic.

14

RF3

RF Throw Port 3. No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the

interface schematic.

18

RF2

RF Throw Port 2. No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the

interface schematic.

22

RF1

RF Throw Port 1. No dc blocking capacitor is required when the RF line potential is equal to 0 V dc. See Figure 4 for the

interface schematic.

24

V2

Control Input 2. See Table 7 for the truth table and Figure 5 for the interface schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground.