KSZ9563R datasheet(48/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 48

 2017-2018 Microchip Technology Inc.

4.5.2

IEEE 1588 PTP MESSAGING PROCESSING

The device supports IEEE 1588 PTP time synchronization when 1588 PTP mode and message detection are enabled.

Different operations will be applied to PTP packet processing based on the setting of P2P or E2E in transparent clock

mode, master or slave in ordinary clock mode, one-step clock mode, and if the domain checking is enabled. For the

IPv4/UDP egress packet, the checksum can be updated by either re-calculating the two-bytes or by setting it to zero.

For the IPv6/UDP egress packet, the checksum is always updated.

4.5.3

IEEE 1588 PTP EVENT TRIGGERING AND TIMESTAMPING

An event trigger output signal can be generated when the target and activation time matches the IEEE1588 PTP system

clock time. Likewise, an event timestamp input can be captured from an external event input signal and the correspond-

ing time on the IEEE1588 PTP system clock will be captured. Both the output event block and the input timestamp block

can be programmed to generate interrupts.

4.6

Clocking

4.6.1

PRIMARY CLOCK

The device requires a 25MHz reference clock input at the XI pin. This clock is internally multiplied up and used to clock

all of the internal logic and switching functions. It is also normally used as to clock the PHY transmit paths. This clock

may be supplied by connecting a crystal between the XI and XO pins (and appropriate load capacitors to ground). Alter-

natively, an external CMOS clock signal may drive XI, while XO is left unconnected. The XI/XO block is powered from

AVDDH.

4.6.2

MAC INTERFACE CLOCKS

The MII interface is clocked asymmetrically, with the PHY device driving both the RX_CLKx receive clock and the TX_-

CLKx transmit clock to the MAC device. The MII port may be configured at reset by a strapping option to take the role

of either the PHY or the MAC. RX_CLK and TX_CLK are therefore either both inputs or both outputs, depending on

the MII mode.

FIGURE 4-9:

PTP SYSTEM CLOCK OVERVIEW

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