ADC9708 datasheet(5/8 Pages) NSC

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Functional Description (Continued)

Auto-Zero and Full-Scale Features

No Zero Offset

TLH10409 – 3

No Full-Scale Error

Count (n) e

VIN

VREF

256

FIGURE 5 Ideal Transfer Function

NFS i 256

TLH10409 – 4

NZ i 0

(N) has both full-scale and zero errors

FIGURE 6 Transfer Function with

Zero and Full-Scale Error

N e N b NZ

TLH10409 – 5

N has Full-Scale Error

FIGURE 7 Transfer Functions with

Zero-Correction Added

TLH10409 – 6

N e (N b NZ) c

256

(NFS b NZ)

FIGURE 8 Transfer Function with both Zero and

Full-Scale Correction Added

Typical Applications

Application Suggestions and Formulas

1 The capacitor node impedance is approximately 30 mX

and should have no parallel resistance for proper opera-

tion

2 tR when VIN e 0V will be finite (ie the comparator will

always toggle for VIN t 0V)

3 The ramp stop output is open collector and an external

pull-up resistor is required

4 All digital inputs and outputs are TTL compatible

5 For proper operation timing commences on the 0 to 1

transition of ramp start and terminates on the 1 to 0 tran-

sition of ramp stop

6 tA t

IA b IR

VREF (See Figure 1 )

7 tR (ramp time) e

VIN tR

lmax e

VREF

(See

Figure 1 )

8 IR e

VCC b VREF

RREF

9 2V s VREF s (VCC b 2V)

10 Address lines A0 A1 A2 must be stable throughout the

sampling interval tA

11 Pin 6 (RREF) should be bypassed to ground via a 002

F capacitor

Microprocessor Considerations

Several alternatives exist from a hardwaresoftware stand-

point in microprocessor based systems using the ADC9708

1 The ramp time measurement may be implemented in

software using a register increment followed by a branch

back depending on the status of the ramp stop

2 Alternately the ramp stop may be tied into the interrupt

structure in systems containing a programmable binary

timer This scheme has the following advantages

a The CPU is not committed during the ramp time inter-

val

b It requires only 5 bits of an IO port for control signals

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