LTC4253IGN datasheet(26/32 Pages) LINER

26 / 32 page

LTC4253

4253f

for reset by pulsing the UV pin or VIN pin, while no initial

timing cycle is generated for reset by pulsing of the TIMER

and SS pins.

Using Reset as an ON/OFF switch

The asynchronous RESET pin can be used as an on/off

function to cut off supply to the external power modules or

loads controlled by the chip. Pulling RESET high will pull

APPLICATIO S I FOR ATIO

(Refer to Block Diagram)

GATE, SS, TIMER and SQTIMER low and the PWRGD

signal high. The supply is fully cut off if the RESET pulse

is maintained wide enough to fully discharge the GATE and

SS pins. As long as RESET is high, GATE, SS, TIMER and

SQTIMER are strapped to VEE and the supply is cut off.

When RESET is released, if VSENSE > VCB, UV < VUVLO, OV

> VOVHI or VIN is in UVLO, the chip waits for the interlock

conditions before recovering as described in the Opera-

UV/OV

TIMER

GATE

SENSE

DRAIN

PWRGD1

PWRGD2

PWRGD3

SQTIMER

EN2

EN3

4 5 67

9A B C

4253 F11

INITIAL TIMING

GATE

START-UP

UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS

UV/OV CLEARS VUVHI, CHECK OV CONDITION, RESET< 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL

UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE

VOVHI

VOVLO

VUVHI

VGATEL

VTMRH

VACL

VSQTMRH

VSQTMRL

VCB

VTMRL

20 • (VACL + VOS)

20 • (VCB + VOS)

20 • VOS

µA

VSQTMRH

VDRNCL

VDRNL

VIN – VGATEH

200

µA + 8 • IDRN

VSQTMRL

Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)

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