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DRA821U2...ALM Folha de dados(PDF) 187 Page - Texas Instruments |
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DRA821U2...ALM Folha de dados(HTML) 187 Page - Texas Instruments |
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187 / 252 page  7.9.5.13 MCAN Table 7-44 and Table 7-45 presents timing conditions and switching characteristics for MCAN. For more details about features and additional description information on the device Controller Area Network Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names, where n represents the specific MCAN module. Table 7-44. MCAN Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 15 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 20 pF Table 7-45. MCAN Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT MCAN1 td(MCAN_TX) Delay time, transmit shift register to MCANn_TX 10 ns MCAN2 td(MCAN_RX) Delay time, MCANn_RX to receive shift register 10 ns For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM. 7.9.5.14 MCASP For more details about features and additional description information on the device Multichannel Audio Serial Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Section 7.9.5.14.1 and Figure 7-77 present timing requirements for MCASP0 to MCASP11. Table 7-46. MCASP Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT Input Conditions SRI Input slew rate 0.7 5 V/ns Output Conditions CL Output load capacitance 1 10 pF PCB Connectivity Requirements td(Trace Delay) Propagation delay of each trace 100 1100 ps td(Trace Mismatch Delay) Propagation mismatch across all traces 100 ps 7.9.5.14.1 Timing Requirements for MCASP NO.1 PARAMETER DESCRIPTION MODE MIN MAX UNIT ASP1 tc(AHCLKRX) Cycle time, AHCLKR/X 15.26 ns ASP2 tw(AHCLKRX) Pulse duration, AHCLKR/X high or low -1.53 + 0.5P2 ns ASP3 tc(ACLKRX) Cycle time, ACLKR/X 15.26 ns ASP4 tw(ACLKRX) Pulse duration, ACLKR/X high or low -1.53 + 0.5R3 ns ASP5 tsu(AFSRX-ACLKRX) Setup time, AFSR/X input valid before ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 www.ti.com DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: DRA821U-Q1 |
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