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DRA821U2...ALM Folha de dados(PDF) 182 Page - Texas Instruments

Nome de Peças DRA821U2...ALM
Descrição Electrónicos  DRA821 Jacinto™ Processors
PDF  252 Pages
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DRA821U2...ALM Folha de dados(HTML) 182 Page - Texas Instruments

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Table 7-40. HyperBus Timing Conditions (continued)
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
tSR
Input slew rate
2
5
V/ns
Output Conditions
CLOAD
Output load capacitance
1.5
10
pF
7.9.5.10.1 Timing Requirements for HyperBus Initialization
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
D1
tw(RESETn)
RESETn Pulse Width
200
ns
D2
tw(csL)
Chip Select Pulse Width
1000
ns
D3
td(RESETnH-csL)
Delay time, RESETn inactive to CSn active
200.34
ns
D4
td(csL-RWDSL)
Delay time, CSn active to RWDS falling
115
ns
7.9.5.10.2 HyperBus 166 MHz Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
D5
tskn(rwdsX-dV)
Input skew, RWDS transitioning to D0:D7 valid
-0.46
0.46
ns
D6
tc(clk/clkn)
CLK period, CLK/CLKn
6
ns
D7
tw(clk/clkn)
Pulse width, CLK/CLKn
2.7
ns
D8
tw(csIV)
Pulse width, CS0 invalid between operations
6
ns
D9
td(clkH-csL)
Delay time, CS0 active to CLK rising/ CLKn falling
-3.34
ns
D10
td(clkL[LE]-csH)
Delay time, last falling CLK/ rising CLKn edge to CS0 inactive
0.41
ns
D11
td(clkX-rwdsV)
Delay time, CLK transition to RWDS valid
1.01
2.08
ns
D12
td(clkX-d[0:7]V)
Delay time, CLK transitioning to D0:D7 valid
0.84
2.17
ns
7.9.5.10.3 HyperBus 100 MHz Switching Characteristics
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
LFD5
tskn(rwdsX-dV)
Input skew, RWDS transitioning to D0:D7 valid
-0.81
0.81
ns
LFD6
tc(clk)
CLK period, CLK
10
ns
LFD7
tw(clk)
Pulse width, CLK
4.75
ns
LFD8
tw(csIV)
Pulse width, CS0 invalid between operations
10
ns
LFD9
td(clkH-csL)
Delay time, CS0 active to CLK rising
-3.51
ns
LFD10
td(clkL[LE]-csH)
Delay time, last falling CLK edge to CS0 inactive
0.51
ns
LFD11
td(clkX-rwdsV)
Delay time, CLK transition to RWDS valid
1.51
3.49
ns
LFD12
td(clkX-d[0:7]V)
Delay time, CLK transitioning to D0:D7 valid
1.34
3.66
ns
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
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