DRA821U2...ALM datasheet(122/252 Pages) TI

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7.9.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,

see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description..

Table 7-4. System Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.9.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset

related signals.

Table 7-5. MCU_PORz Timing Requirements

see Figure 7-10

NO.

MIN

TYP

MAX UNIT

RST1

th(MCUD_SUPPLIES_VALID - MCU_PORz)

Hold time, MCU_PORz active (low) at Power-

up after all MCU DOMAIN supplies valid (using

external crystal)

N +

1200(2)

9500000

RST2

Hold time, MCU_PORz active (low) at Power-

up after all MCU DOMAIN supplies(1) valid and

external clock stable (using external LVCMOS

oscillator)

1200

RST3 tw(MCU_PORzL)

Pulse Width minimum, MCU_PORz low after

Power-up (without removal of Power or system

reference clock MCU_OSC0_XI/XO)

1200

(1)

For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence TBD.

(2)

N = oscillator start-up time

MCU_PORz

RST1

RST3

MCU_OSC0_XI,

MCU_OSC0_XO

RST2

MCU DOMAIN

SUPPLIES VALID

Figure 7-10. MCU_PORz Timing Requirements

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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