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combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal

circuit components to OSC1 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB designer

should be able to extract mutual parasitic capacitance between these signal traces. The device package also

has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined in Table 7-21.

PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is

typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can

also be minimized by placing a ground trace between these signals when the layout requires them to be routed

in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as

possible when selecting a crystal.

J7ES_AUX_OSC_SC_06

Device

OSC1_XO

OSC1_XI

PCBXIXO

PCB

Signal Traces

Crystal Circuit

Components

XIXO

Figure 7-32. Shunt Capacitance

A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt

capacitance specified by the crystal manufacturer.

Cshunt ≥ CO + CPCBXIXO + CXIXO

For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω,

CPCBXIXO = 0.7 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.29 pF.

7.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source

Figure 7-33 shows the recommended oscillator connections when OSC1_XI is connected to a 1.8-V LVCMOS

square-wave digital clock source.

Note

A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not

allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state

when DC is applied to the input. Therefore, application software should power down OSC1 any time

OSC1_XI is not toggling between logic states.

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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