48LM01 datasheet(8/40 Pages) MICROCHIP

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DS20006008C-page 8

48L512/48LM01

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

2.1

Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

When the device is deselected, SO goes to the

high-impedance state, allowing multiple parts to share

the same SPI bus. A low-to-high transition on CS after

a valid write sequence completes the SRAM write

cycle. After power-up, a high-to-low transition on CS is

required prior to any sequence being initiated.

2.2

Serial Output (SO)

The SO pin is used to transfer data out of the

48L512/48LM01. During a read cycle, data is shifted

out on this pin after the falling edge of the serial clock.

2.3

Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses, and data. Data is

latched on the rising edge of the serial clock.

2.4

Serial Clock (SCK)

The SCK is used to synchronize the communication

between

master

and

the

48L512/48LM01.

Instructions, addresses, or data present on the SI pin

are latched on the rising edge of the clock input, while

data on the SO pin is updated after the falling edge of

the clock input.

2.5

Hold (HOLD)

The HOLD pin is used to suspend transmission to the

48L512/48LM01 while in the middle of a serial

sequence without having to retransmit the entire

sequence over again. It must be held high any time this

function is not being used. Once the device is selected

and a serial sequence is underway, the HOLD pin may

be pulled low to pause further serial communication

without resetting the serial sequence.

The HOLD pin should be brought low while SCK is low,

otherwise the Hold function will not be invoked until the

next SCK high-to-low transition. The 48L512/48LM01

must remain selected during this sequence. The SI and

SCK levels are “don’t cares” during the time the device

is paused and any transitions on these pins will be

ignored. To resume serial communication, HOLD pin

should be brought high while the SCK pin is low,

otherwise serial communication will not be resumed

until the next SCK high-to-low transition.

The SO line will tri-state immediately upon a

high-to-low transition of the HOLD pin, and will begin

outputting again immediately upon a subsequent

low-to-high transition of the HOLD pin, independent of

the state of SCK.

TABLE 2-1:

PIN FUNCTION TABLE

Name

8-Lead SOIC

8-Lead SOIJ

Description

Chip Select Input

Serial Data Output

VCAP

External Capacitor

VSS

Ground

Serial Data Input

SCK

Serial Clock Input

HOLD

Hold Input

VCC

Supply Voltage

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