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VND9012AJ Folha de dados(PDF) 3 Page - STMicroelectronics |
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VND9012AJ Folha de dados(HTML) 3 Page - STMicroelectronics |
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3 / 40 page ![]() 1 Block diagram and pin description Figure 1. Block diagram Logic VCC Gate driver CH 1 CH 0 VCC-OUT clamp limitation Current Power limitation Overtemperature Open-Load in OFF Reverse battery Sense Current Channel 0 control & diagnostic Channel 1 shut-down Undervoltage Internal supply clamp VCC – GND GND SEL IN0 IN1 SEn FaultRST OUT0 OUT1 CS GADG0507181254PS Table 1. Pin functions Name Function VCC Battery connection. OUTPUT0,1 Power output. GND Ground connection. Must be reverse battery protected by an external diode / resistor network. INPUT0,1 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. CS Multiplexed analog sense output pin; it delivers a current proportional to the selected load current. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin. SEL Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer. FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. VND9012AJ Block diagram and pin description DS12727 - Rev 3 page 3/40 |
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