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WM8590GEDS/V Folha de dados(PDF) 20 Page - Wolfson Microelectronics plc |
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WM8590GEDS/V Folha de dados(HTML) 20 Page - Wolfson Microelectronics plc |
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20 / 51 page ![]() WM8590 Pre-Production w PP Rev 3.3 September 2005 20 LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB Figure 12 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB of DIN is sampled by the WM8590 on the rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 13). LEFT CHANNEL RIGHT CHANNEL DACLRC/ ADCLRC DACBCLK/ ADCBCLK DIN/ DOUT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB Figure 13 Right Justified Mode Timing Diagram |
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