ST7LNB0

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2 ST7LNB0 IMPLEMENTATION

The following figure shows a typical application circuit for the ST7LNB0:

Figure 3 ST7LNB0 typical application circuit

Notes:

1.The divider chain connected to the DRX pin must have the following resistance values: 330K

100K

2.The reset circuitry linked to the RESET pin is optional, in fact the ST7LNB0 has an internal voltage level

detector LVD which generates a static reset when the VDD supply is below a threshold voltage of 4.1 V.

3.The DiSEqC signalling must have a tone frequency of 22KHz(+/- 20%) and an amplitude exceeding 150

mV peak to peak.

4. When the LVD is enabled (default state), it is mandatory not to connect a pull-up resistor. A 10nF pull-

down capacitor is recommended to filter noise on the reset line.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ST7LNB0

CONTROL

F-CONNECTOR

10n

100K

330K

LNB / SWITCHER

CONTROL

SBY

LNB / SWITCHER

(Uncommitted SW)

(Committed SW)

2.2 nF

2N2222

OPTIONAL

1