A Product Line of

Diodes Incorporated

PI2DPX2023

13

www.diodes.com

July 2022

Diodes Incorporated

PI2DPX2023

Document Number DS43532 Rev 4-2

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Units

VTX-DIFFp-p-

Level0

Differential peak-to-peak output

voltage swing Level 0

Tested with Pre-emphasis at

Level 0= 0dB

Level 1= 3.5dB

Level 2= 6.0 dB

0.34

0.4

0.46

V

VTX-DIFFp-p-

Level1

Differential peak-to-peak output

voltage swing Level 1

0.51

0.6

0.68

V

VTX-DIFFp-p-

Level2

Differential peak-to-peak output

voltage swing Level 2

0.69

0.8

0.92

V

Tj TX Total

Jitter

UHBR20(20Gbps) TP2

Measured at Transmit output.

Prechannel loss from 2.5dB

to 13dB

—

—

0.45

UI

UHBR13(13.5Gbps) TP2

—

—

0.45

UI

UHBR10(10Gbps) TP2

—

—

0.38

UI

HBR3 (8.1Gbps)

—

—

0.27

UI

HBR2 (5.4Gbps)

—

—

0.27

UI

HBR (2.7Gbps)

—

—

0.294

UI

RBR (1.62Gbps)

—

—

0.18

UI

AUX Listener Electrical Specification

Cin

Input capacitance at , AUXP or

AUXN

—

—

10

pF

VT(AUX_lis-

tener)

Threshold of the AUX listener

VCC = 1.8V

100

—

220

mVPPd

Note:

1. Measured using a vector-network analyzer (VNA) with -30dBm power level applied to the adjacent input. The VNA detects the signal at the output of the victim

channel. All other inputs and outputs are terminated with 50Ω.

2. Subtract the channel gain from the total gain to derive the actual crosstalk

AC/DC Characteristics Cont.

Control Pin Specifications

(VDD = 1.8 ± 5%, TA = -40°C to 85°C)

Symbol

Parameter

Min.

Typ.

Max.

Units

2-level Control Pins

VIH

DC input logic high

VDD*0.65

—

—

V

VIL

DC input logic low

—

—

VDD*0.35

V

IIH

Input high current

—

—

50

uA

IIL

Input Low current

-50

—

—

uA

4-level Control Pins

VIH

DC input logic “High”

0.92*VDD

VDD

—

V

VIF

DC input logic “Float”F

0.59*VDD 0.67*VDD 0.75*VDD

V

VIR

DC input logic “With Rext to GND” R

0.25*VDD 0.33*VDD 0.41*VDD

V

VIL

DC input logic “Low”

—

GND

0.08*VDD

V

IIH

Input high current

—

—

50

uA