5.4

Valley-lock feature

When the system operates in the valley skipping-mode, uneven switching cycles may be observed under some

line/load conditions, due to the fact that the off-time of the GaN is allowed to change with discrete steps of one

ringing cycle, while the off-time needed for cycle-by-cycle energy balance may fall in between. Thus, one or more

longer switching cycles are compensated by one or more shorter cycles and vice versa.

This “valley-jump” phenomenon introduces a low-frequency component in the primary current that may fall in the

audible range and if this periodic perturbation is sufficiently large in amplitude, audible noise can be generated by

mechanical vibrations of the magnetic components.

To avoid this phenomenon a new patent-pending valley-lock feature is implemented that, for a certain input

voltage and output load condition, fixes the number of skipped valleys during valley skipping mode operation,

regardless of the DC bus voltage ripple.

The function is disabled when the VFB falls below 1.3 V and re-enabled again when VFB increases up to 1.43 V

(typ.)

5.5

Constant voltage operation and burst-mode

The FB pin is connected to an optocoupler which transmits the error signal from the regulation loop located on the

secondary side of the converter, see Figure 13. Typically, a TS431 is used as a voltage reference.

The FB pin is driven directly by the phototransistor's collector to modulate the duty cycle.

A capacitor across the pin is usually used to compensate the loop.

When the FB pin voltage falls 60 mV below VFBB, the GaN is turned OFF and the IC consumption is reduced to IQ

to minimize the bias losses.

After the GaN turns OFF, the FB pin voltage increases as a reaction to the interruption of the energy delivery, and

as it reaches VFBB the device starts switching again.

The effect of this burst-mode operation, shown in Figure 14, is to reduce the equivalent switching frequency,

which can go down even to few hundred hertz, minimizing all frequency related losses and making it easier to

comply with energy saving regulations. Also the low peak current ensures noise free operations.

Figure 13. Constant output voltage control principle: internal schematic and pin configuration

VIPERGAN65

Valley-lock feature

DS14005 - Rev 2

page 14/35