Preliminary Technical Data

AD7794

REV.PrE 6/04 | Page 13

Pin

No.

Mnemonic

Function

AIN5(-) is the negative terminal of the differential analog input pair AIN5(+)/AIN5(-).

Alternatively, the internal excitation current source can be made available at this pin. The excitation current

source is programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be

switched to this output.

17

AIN4(+)/REFIN2(+)

Analog Input/Positive Reference Input.

AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(-).

The nominal reference voltage (REFIN2(+) – REFIN2(–)) is 2.5 V, but the part functions with a reference from 0.1

18

AIN4(-)/REFIN2(-)

Analog Input/Negative Reference Input.

AIN4(-) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(-).

This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere

19

PSW

Low Side Power Switch to GND.

20

GND

Ground Reference Point.

21

Supply Voltage, 2.7 V to 5.25 V.

22

23

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output pin

to access the output shift register of the ADC. The output shift register can contain data from any of the

on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin,

going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go

high before the next update occurs.

The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.

With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word

informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.

The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY

pin is three-stated but the RDY bit remains active.

24

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control

registers within the ADC, the register selection bits of the communications register identifying the appropriate

register.