LEE-128G032B-2

www.vishay.com

Vishay Dale

Revision: 07-Dec-12

2

Document Number: 37097

For technical questions, contact: displays@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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INTERFACE SIGNAL DESCRIPTION

Dot clock - This signal enters the serial data on each low to

high transition. A total of 128 dot clock transitions must be

present for each line of column/anode data.

Serial data - This signal presents the pixel data in positive

logic format. A logic one represents a lit pixel and a logic

zero represents an extinguished pixel. Data is entered from

right to left. The first pixel data entered will represent the left

most pixel in the row.

Column latch - This signal latches the pixel data into the

driver outputs. When the column latch signal goes to logic

one the data entered previously will fall through to the driver

outputs. When the signal returns to a logic zero the data is

latched and the shift register is now ready to accept the next

row of data. Must be held low while entering new serial data.

Display enable - This signal enables the output drivers.

Using a duty cycle control, this signal may also be used for

intensity control. The display enable must be at logic zero

before the column latch signal transitions. To avoid display

blurring, the row clock signal should also transition while

display enable is a logic zero.

Row data - This signal is the first line marker for the scan.

This input should be held high to correspond to the first row

of pixel data.

Row clock - This signal clocks row data on the falling edge.

The row clock signal is repetitive and must be present for

proper scanning of the display module.

The LEE-128G032B-2 has an unique input protection circuit

that assures the column drivers stay blanked on power up.

The protection circuit unblanks the column drivers when the

row clock signal begins (i.e the display begins scanning).

PIN DESCRIPTION

J2 - POWER CONNECTOR

Molex 26-48-1045 or equivalent.

Mates with Tyco AMP 3-640428-8, or Molex 09-50-3041

housing with 08-50-0106 socket crimp terminals or equivalent.

PIN

SIGNAL

DESCRIPTION

1VCC

Logic and LED drive supply

2VCC

Logic and LED drive supply

3

GND

Ground

4

GND

Ground

J1 - DATA CONNECTOR

FCI 75869-102LF or equivalent.

Mates with Tyco AMP 1658621-2 or equivalent

PIN

DESCRIPTION

PIN

DESCRIPTION

1

Display enable

2

Ground

3

Row data

4

Ground

5

Row clock

6

Ground

7

Column latch

8

Ground

9

Dot clock

10

Ground

11

Serial data

12

Ground

13

No connection

14

Ground

LOGIC AND DATA TIMING

PARAMETER

MIN.

TYP.

MAX.

UNITS

t1

100

-

-

ns

t2

5-

-

μs

t3

1-

-

μs

t4

-

70

200

Hz

t5

25

-

-

ns

t6

75

-

-

ns

t7

75

-

-

ns

ORDERING INFORMATION

DESCRIPTION

PART NUMBER

Display, Driver Electronics and

+ 5 V HC CMOS Interface

LED-128G032B-2

J1 Data Connector Kit

(2 pcs. recommended)

280105-08

J2 Power Connector Kit

280108-16

Row Clock

Column Latch

Display Enable

Row Data

t

4

Display Enable

2

1

030

31

0

1

Serial Data

2

1

0

126 127

1

st bit of row will appear in left most column

t

2

Row Clock

230

31

0

1

1

0

t

3

t

1

t

5

Dot Clock

Positive edge x 128

t

6

t

7